EET 1131 Unit 7 Arithmetic Operations and Circuits Read Kleitz, Chapter 7, skipping Sections 7-4, 7-5, and 7-8. Homework #7 and Lab #7 due next week. Quiz next week. Binary Addition The rules for binary addition are 0+0=0 Sum = 0, carry out = 0 0+1=1 Sum = 1, carry out = 0 1+0=1 Sum = 1, carry out = 0 1 + 1 = 10 Sum = 0, carry out = 1 When a carry in = 1 due to a previous result, the rules are 1 + 0 + 0 = 01 1 + 0 + 1 = 10 1 + 1 + 0 = 10 1 + 1 + 1 = 11 Sum = 1, carry out = 0 Sum = 0, carry out = 1 Sum = 0, carry out = 1 Sum = 1, carry out = 1 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Binary Addition Add the binary numbers 00111 and 10101 and show the equivalent decimal addition. 0111 00111 10101 7 21 11100 = 28 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Binary Subtraction, Multiplication, Division The textbook also gives rules for doing binary subtraction, multiplication, and division. From a practical standpoint, though, it’s easier to do one of the following: Either convert the numbers from binary to decimal, then perform the arithmetic operation, then convert back to binary. Or use Windows Calculator to perform these operations directly on binary numbers. Half-Adder Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry out and Sum). The inputs and outputs can be summarized on a truth table. Inputs Outputs A 0 0 1 1 B 0 1 0 1 Cout 0 0 0 1 S 0 1 1 0 The logic symbol and equivalent circuit are: A S S S A B Cout B Cout © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Full-Adder Inputs By contrast, a full adder has three binary inputs (A, B, and Carry in) and two binary outputs (Carry out and Sum). The truth table summarizes the operation. A full-adder can be constructed from two half adders as shown: A A S S A S S A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Outputs Cin 0 1 0 1 0 1 0 1 Cout 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1 Sum S B B Cout B A Cout B Cin Cin Cout S Cout Symbol for Full Adder © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Full-Adder 1 A 0 B For the given inputs, determine the intermediate and final outputs of the full adder. S S 1 A Cout 0 B S S 0 Cout 1 1 Sum Cout 1 The first half-adder has inputs of 1 and 0; therefore the Sum =1 and the Carry out = 0. The second half-adder has inputs of 1 and 1; therefore the Sum = 0 and the Carry out = 1. The OR gate has inputs of 1 and 0, therefore the final carry out = 1. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Full-Adder Notice that the result from the previous example can be read directly on the truth table for a full adder. Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Outputs Cin 0 1 0 1 0 1 0 1 Cout 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1 1 A 0 B 1 S S 1 A Cout 0 B S S 0 Cout 1 Sum Cout 1 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Convention for Writing Multi-Bit Numbers We’ll use subscripts to refer to the individual bits in a binary number. The bit on the right-hand end, or least significant bit (LSB), always gets the smallest subscript, which may be either 1 or 0. Example: In a four-bit number A, the bits are labeled either A4A3A2A1 or A3A2A1A0 Parallel Adders Full adders are combined into parallel adders that can add binary numbers with multiple bits. A 4-bit adder is shown. A4 B4 A3 B3 A2 B2 A1 B1 C0 A B Cin Cout S C4 S4 A B Cin Cout C3 S S3 A B Cin Cout C2 S S2 A B Cin Cout C1 S S1 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Parallel Adders The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a Carry In (labeled C0) and a Carry Out (labeled C4). Binary number A Binary number B Carry In 1 2 3 4 1 2 3 4 C0 S 1 2 3 4 C4 4-bit sum Carry Out The 74283 is an example. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Two Adder Chips 74283 Four-bit binary adder 7483 is an older chip that is functionally identical to the 74283, but the pins are laid out differently Cascading Parallel Adders When we connect the outputs from one circuit to the inputs of another identical circuit to expand the number of bits being operated on, we say that the circuits are cascaded together. For example, you can cascade two 4-bit parallel adders to add two 8-bit numbers. To do this, connect the lowerorder adder’s Carry Out to the higher-order adder’s Carry In. See textbook’s Figure 7-18 (next slide). © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Arithmetic Logic Unit (ALU) Central to any computer system is its ALU, which performs mathematical and logical operations on data. In modern systems, the ALU is contained on the computer’s microprocessor chip. In older systems, the ALU was a separate chip, such as the 74181. How Many Logical Operations? You already know how to perform some logical operations on two input bits, A and B. Examples: X = AB X = A+B Question: How many possible logical operations are there on two input bits? How Many Logical Ops? (Continued) A B 0 0 0 1 1 0 1 1 Let’s list them all: 74181 ALU chip Can perform 16 logical operations (bitby-bit) and 16 arithmetic operations on two 4-bit input numbers. Data Sheet: 74LS181 See next slide (Fig. 7-27 from textbook) for logic symbol and function table. Figure 7.27 The 74181 ALU: (a) logic symbol; (b) function table. Digital Electronics: A Practical Approach with VHDL, 9th Edition William Kleitz Copyright ©2012 by Pearson Education, Inc. All rights reserved. 74181 ALU (Continued) Caution: In the “Arithmetic Operations” columns of the 74181 function tables, the + symbol always means logical OR, not addition. The word “PLUS” is used for addition. 74181 ALU (Continued) Fourteen Input Pins: A0 to A3 form one of the 4-bit inputs. B0 to B3 form the other 4-bit input. CN is the carry-in bit, used only during arithmetic ops (ignored during logic ops). M is the mode pin (arithmetic or logic). S0 to S3 select the operation performed. 74181 ALU (Continued) Eight Output Pins: F0 to F3 form the 4-bit output. CN+4 is carry-out bit, meaningful only for arithmetic ops. (Ignore it for logic ops.) A=B is comparison bit, meaningful only when performing “A MINUS B” operation. (We’ll ignore this.) P and G are carry-look-ahead bits for high-speed arithmetic, when 74181 is used in conjunction with 74182 chip. (We’ll ignore these.) Terminology: One’s-Complement and Two’s-Complement The one’s-complement of a binary number is the binary number that you get when you invert each bit. Example: What is the one’s-complement of 00110101? The two’s-complement of a binary number is the binary number that you get when you invert each bit and then add 1 to the result. What is the two’s-complement of 00110101? Interpreting Strings of 1s and 0s In digital systems we have nothing but 1s and 0s to represent all kinds of info: text, numbers, images, music, etc. To interpret a string of 1s and 0s, you have to be told what kind of info it represents. Example: What does 010000012 represent? Possible answers: The number 65. The letter A (in ASCII code). … Unsigned versus Signed Binary Integers Up to now, whenever we’ve worked with binary numbers, we’ve assumed they were unsigned binary integers. In other words, we’ve assumed that the numbers were all positive. Sometimes we also need to be able to represent negative integers, in which case we’re dealing with signed binary integers. To do this, we’ll use one bit to indicate the number’s sign (positive or negative). Range of Unsigned Binary Integers Arranging unsigned 8-bit integers in order from least to greatest would give you a list that starts and ends like this: Binary 00000000 00000001 00000010 11111101 11111110 11111111 Decimal 0 1 2 253 254 255 Range of Unsigned Binary Integers For unsigned integers with a fixed number of bits n: The least integer we can represent is 0. The greatest integer we can represent is 2n-1. Example: Using 8 bits, The least integer is 000000002, which is equal to decimal 0. The greatest integer is 111111112, which is equal to decimal 255 (=28-1). Representing Signed Binary Integers To represent both positive and negative integers, we use the leftmost bit as a sign bit, like this (for 8 bits): Negative integers (sign bit = 1) Zero and positive integers (sign bit = 0) Binary 10000000 10000001 10000010 11111111 00000000 00000001 01111110 01111111 Decimal -128 -127 -126 -1 0 1 126 127 Two’s-Complement Representation The scheme shown on the previous slides is called two’s-complement representation. This is how computers represent signed integers, because this scheme results in simple circuits for doing binary arithmetic. Other common names for it: two’s complement notation or two’s complement form. Range of Signed Binary Integers For signed integers with a fixed number of bits n, the least integer we can represent is −2n−1, and the greatest integer we can represent is 2n−1−1. Example: Using 8 bits, The least integer we 100000002, which is −128 (= −27). The greatest integer 011111112, which is 127 (= 27-1). can represent is equal to decimal we can represent is equal to decimal Steps for Converting from Decimal to Two’s-Complement Form 1. 2. If the integer is positive, convert it to binary as we’ve always done. If the integer is negative: a) b) c) Ignoring the sign, convert it to binary as we’ve always done. Invert each bit. (That is, change each 0 to 1, and change each 1 to 0.) Add 1 to the result. Examples Convert 2310 to two’s complement form using 8 bits. Convert −2310 to two’s complement form using 8 bits. Steps for Converting from Two’sComplement Form to Decimal 1. 2. If the sign bit = 0, the integer is positive. Convert to decimal as we’ve always done. If the sign bit = 1, the integer is negative. Follow these steps: Invert each bit. b) Add 1. c) Convert the result to decimal as we’ve always done. d) Write a negative sign in front. Examples: Convert 01100010 to decimal. Convert 11100010 to decimal. a) Adding Signed Numbers Using two’s complement form for negative integers simplifies addition and subtraction of signed numbers. Rules for addition: Add the two signed numbers. Discard any final carry out of the MSB. The result is in two’s complement form. Examples: 00011110 30 + 00001111 + 15 00101101 45 00001110 14 +11101111 + -17 11111101 -3 11111111 -1 + 11111000 + -8 111110111 -9 Discard carry © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Subtracting Signed Numbers Rules for subtraction: Negate the number being subtracted, and then add. Discard any final carry out of the MSB. The result is in two’s complement form. Us the same numbers as on previous slide, but subtract: 00011110 30 - 00001111 – 15 00001110 14 - 11101111 – -17 11111111 -1 - 11111000 – -8 Negate the number being subtracted, and then add: 00011110 30 +11110001 +-15 100001111 15 Discard carry 00001110 14 + 00010001 +17 00011111 31 11111111 -1 + 00001000 + 8 100000111 7 Discard carry © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved An Adder/Subtractor Circuit By combining parallel adder chips (such as the 74283 or the 4008) with a controlled inverter, we can make a circuit that either adds or subtracts, depending on the value of a control input. See next slide (Fig. 7-23 from textbook). Figure 7.23 8-bit two’s-complement adder/subtractor illustrating the subtraction 42 – 23 = 19. Digital Electronics: A Practical Approach with VHDL, 9th Edition William Kleitz Copyright ©2012 by Pearson Education, Inc. All rights reserved.

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